1. Field of the Invention
The invention relates to a method for fabricating a gate dielectric layer, and more particularly a dual gate dielectric layer.
2. Description of the Related Art
A gate dielectric layer, such as silicon oxide layer, is a dielectric formed under a gate of a MOS. MOS evokes electric charge in a channel through the gate dielectric layer, improving the quality of the gate dielectric layer.
FIGS. 1a to 1e are cross-sections of a conventional method for fabricating a gate with a gate dielectric layer;
In FIG. 1a, a semiconductor substrate 101, such as silicon substrate, is provided. A dielectric layer 102, such as pad oxide layer, a hard mask layer 103, such as LPCVD nitride layer, and a patterned photoresist layer 104 with an opening 105 are sequentially formed on the surface of the semiconductor substrate 101, wherein the position of the opening 105 is the position a gate formed in the subsequent process.
In FIG. 1b, the hard mask layer 103 is etched to form an opening 106 using the patterned photoresist layer 104 as a mask, wherein the opening 106 exposes the surface of the semiconductor substrate 101.
In FIG. 1c, the semiconductor substrate 101 is thermally oxidized to form a gate dielectric layer 107, such as gate oxide layer, on the bottom surface of the opening 106.
In FIG. 1d, a conducting layer 108, such as polysilicon or epi-silicon, is formed on the hard mask layer 103, wherein the opening 106 is filled with the conducting layer 108.
In FIG. 1e, the conducting layer 108 is planarized to expose the surface of the hard mask layer 103. The hard mask layer 103 and the dielectric layer 102 are sequentially removed to leave the conducting layer 108a as a gate. S/D area is formed in the semiconductor substrate 101 in the subsequent process, and a MOS with gate with the gate dielectric layer 107 is complete.
The conventional method will fabricate a MOS with one gate dielectric thickness. The thickness of the gate dielectric layer is less when the size of the element is reduced. In order to reduce the GIDL (gate induced gate leakage) effect and gate to S/D leakage, after gate patterned, the gate is oxidized to gain a thicker dielectric thickness at the gate edge. This traditional gate re-oxidation method is hard to control the mini-bird-beak length into the gate at the gate edge. In this invention, a dual gate dielectric thickness to achieve thin dielectric thickness at gate center and thick dielectric thickness at gate edge is fabricated. The gate length of thick gate dielectric can be precisely controlled with a spacer implant mask, which means the device performance can be précised controlled. Device fabrication with more process window will be achieved with the two independent gate dielectric thickness fabrication at the same time.